От: fpga journal update [news@fpgajournal.com]
Отправлено: 25 мая 2005 г. 0:32
Кому: Michael Dolinsky
Тема: FPGA Journal Update Vol VII No 8


a techfocus media publication :: May 24, 2005 :: volume VII, no. 08


FROM THE EDITOR

This week, eASIC, Flextronics, and Magma Design Automation announced availability of their Easy eFlow tools suite supporting the new FlexASIC structured ASIC family. Our first feature article takes a look under the hood at the potentially game-changing technology behind FlexASIC, and how it could alter the dynamics of the structured ASIC and high-end FPGA markets. FlexASIC is scheduled for production later this year, so now is a good time for the tools to be rolling out to give design teams a head start preparing for this possibly disruptive silicon technology.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal


LATEST NEWS

May 24, 2005

FlexASIC™ Broadens Appeal by Adding Magma Blast Create SA Support to Enhance Performance and Design Flexibility

Synopsys i-Virtual Stepper System for Photomask Qualification Implemented by UMC

LSI Logic Eliminates Mask Charges for Entry Level Platform ASIC Solutions

May 23, 2005

Initial Wave of Intellectual Property Support For New LatticeXP FPGA Family Now Available

FS2 Introduces System Navigator for the New AMD Geode LX 800@0.9W Processor; Debug That Will Enable Next Generation of Mobile Applications

Celoxica ESL Tool Gets Faster and More Physical; The Leading ESL Design Suite for Algorithm Acceleration Sets New Standards in Performance and Ease-of-Use, Optimizes the Connection to SoC Flows

Cypress Introduces Industry's First 2.4-GHz Radio-on-a-Chip with Programmable Mixed Signal Array; Programmable Radio-on-a-Chip Melds Two Blockbuster Cypress Technologies -- WirelessUSB and PSoC

Xilinx Improves Performance and Productivity for Virtex-4 Platform FPGA Designs With PlanAhead 7.1 Tool

May 20, 2005

Nu Horizons Electronics Corp. Announces Availability of Embedded Development Kit -EDK- 7.1i Featuring New Xilinx MicroBlaze-TM- 4.0 Soft Processor

May 19, 2005

Xilinx Strengthens DSP IP Library With New Floating-Point and Digital Video Broadcasting S2 Cores

Lockheed Martin X-35 Chief Test Pilot Delivers Keynote Address at The MathWorks International Aerospace and Defense Conference

May 18, 2005

FishTail Joins Synopsys in-Sync Program

Nallatech Simplifies Digital Communication System Development With Launch of New Virtex-4 XtremeDSP Development Kit

Memec Simplifies Programmable Systems Design With New Mini-Modules; Complete Embedded Processor System Available on Small Module; Thumb-Size Modules Include Xilinx Virtex-4 or Spartan-3 FPGA; Daughterboard Can be Dropped Into Early-Production System

Actel Quality Program Receives STACK Certification

Now Shipping: New Cyclone II Development Kits for Nios II Embedded Processor, DSP, and PCI Designs

CURRENT FEATURE ARTICLES

Redefining Structured ASIC

eASIC's Better Idea
Pedal to the Metals
A Crash Course in High-Speed Design
Selecting the FPGA that Meets Your Signal Integrity Requirements
by Lalitha Oruganti, Sr. Product Marketing Engineer, FPGA Products, Altera Corporation
World's Best FPGA Article
Up to 53% More Interesting
Mayday Mayhem
FPGA Announcements Galore
The Programmable Base Station
by David Gamba, Senior Marketing Manager, Strategic Solutions Marketing, Xilinx
Power
Suddenly, We Care


Redefining Structured ASIC
eASIC's Better Idea

In most markets, there exist a set of de-facto rules. Sport-utility vehicles have bad fuel economy. Economy cars have limited cargo space. FPGAs use too much power. ASICs have staggering non-recurring engineering (NRE) costs. Generally, the players play by those rules, and the consumer enters every buying decision with a pre-defined understanding of the tradeoffs those rules imply and which basic option favors their situation. The final choice is then decided by a comparison of the less-critical factors that differentiate the products in each area. Once a design team has decided to go with a zero-NRE solution, for example, they typically find themselves comparing various FPGA offerings to find the one that best fits their needs.

Occasionally, however, someone breaks the rules. What if you could get an ASIC with near zero NRE? Would you still be locked into an FPGA solution? What if a structured ASIC offered you some degree of reprogrammability, or if you could vary the design on a small lot basis? Your decision approach, and even your entire design, might shift dramatically.

eASIC has announced its new FlexASIC family of structured ASIC devices that break the established rules. FlexASIC offers density, performance, and power consumption that come close to cell-based ASIC, with flexibility, NRE, and risk avoidance much closer to the FPGA end of the spectrum. This is accomplished by using an innovative architecture that combines FPGA-like look up table (LUT) cells connected by metal routing that is customized by a single via layer. This single via layer can be e-beam programmed for small production runs, or mask programmed for higher volumes.

An additional advantage of the e-beam programming approach is the ability to easily segment wafers, putting multiple design variants on a single wafer. This eliminates minimum volume requirements and ultimately lowers unit costs as a single production lot can be shared across many designs. While e-beam has suffered a somewhat dubious reputation in the past for impractical levels of performance, eASIC points out that their use of e-beam is comparatively fast because only a single via layer is being customized. When it comes time to go to production, no requalification is necessary because the mask-customized version will be identical to the e-beam version.

From a security perspective, FlexASIC also offers the best of both worlds. The via-based routing makes reverse-engineering of the routing fabric extremely difficult, and because the logic is bitstream programmed, the device itself does not contain the entire design until runtime. Potential thieves would have to recreate both elements to have a viable copy of the design. [more]

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